Self-Timed Realization of Combinational Logic

A novel synthesis method for self-timed realization of arbitrary combinational logic functions is presented in this paper. The cost of self-timed implementation of a large number of conventional combinatorial benchmarks is provided. A new self-timed system configuration is also proposed in support of the synthesis heuristic that generally favors weakly indicating realizations of combinational logic. The proposed two-level synthesis technique forms a good starting point for the multi-level synthesis of weakindication circuits and certain preliminary insights in this regard are highlighted.